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Part 4 : VIA & LCD Testing

                  Eagle: v1.2 Schematic                 Eagle: v1.2Board Layout      Gerber Viewer: v1.2 PCB Layout    

 

 

Video: VIA-LCD Code Execution at $7FE0 on v1.2 Breadboard S.B.C.

 

 

2004A 4x20 LCD Display

This v1.2 design is slightly different from v1.0.

Features include:

 - onboard variable 1-100Hz clock as well as a fixed 1MHz clock (crystal oscillator)

 - selectable addressing for VIAs, UARTS, etc.

 

Pullup Resistors

3.3K pullups were added to the CPU, etc.

 

Addressing the VIA & LCD:

v1.0 of the CPU board was for an I/O address of $6000 that was accomplished with this clickable circuit:

That design ran fine with the variable clock and the 1MHz clock.

 

 

v1.2 of the CPU board was for an I/O address starting at $7F00 that is carved up into 8 blocks of 32 addresses, as shown in this clickable circuit:

That design also ran fine with the variable clock and the 1MHz clock.

Addresses starting at $7FE0 are for the VIA and LCD.

Addresses starting at $7FC0 are for the ACIA UART.

Addresses starting at $7FA0 for the 16c550 UART.

Addresses starting at $7F80 will be for the second VIA or whatever.

 

v1.3 of the CPU board is also for an I/O address of $7F00 in blocks of 0x0020 but it uses fewer components; much of the glue logic was replaced with a CD4068BE 8-input single-channel AND/NAND gate operating in AND mode. It selects addresses starting at 0x7F00 and the 74138 mux breaks them out into 0x20 blocks. Additionally, address block allocation starts at 0x7F00 instead of 0x7FE0 as in the previous design.

 

 

This is a work in progress and will change with each revision, the first one being v1.3.

 

 

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