; Z180/64180 INTERNAL REGISTERS 
;
CNTLA0		EQU	0	; ASCI Control Register A 0.
; 8 bits L to R are: MPE, RE, TE, !RTS0, MPBR/EFT, MOD2, MOD1, MOD0
CNTLA1		EQU	1	; ASCI Control Register A 1.
; 8 bits L to R are: MPE RE TE -- MPBR/EFR MOD2 MOD1 MOD0
; RE: Receiver Enable, bit 6, when set to 1 the ASCI transmitter is enabled.
; TE: Transmitter Enable, bit 5, when set to 1 the ASCI receiverer is enabled.
; !RTS0: Request to Send Channel 0 (bit 4 in CNTLA0 only), when 0 it allows ASCI to flow control the other end.
; MPBR/EFR: disable, used with multiprocessor mode. EFR = Error Flag Reset.
; MODs determine data formats. 8|N|1 = 1|0|0. See manual page 42.
; 7 6 5 4 3 2 1 0
; 0 1 1 0 0 1 0 0
CNTLB0		EQU	2
; 8 bits L to R are: MPBT, MP, !CTS/PS, PEO, DR, SS2, SS1, SS0
; 7 6 5 4 3 2 1 0	Manual page 44.
; 0 0 x x 0 1 1 1
CNTLB1		EQU	3
STAT0		EQU	4	; ASCI Status Register 0, to interrogate communication, error and modem control signal status,
                    ; and enabling/disabling of ASCI interrupts.
; 8 bits L to R are: RDRF, OVRN, PE, FE, RIE, !DCD0, TDRE, TIE			
; RDRF is set to 1 when an incoming byte is loaded into an empty Rx FIFO. It is cleared by reading RDR.
; OVRN: Overrun Error, bit 6, if no room for received character because Rx FIFO is full. 
; It is cleared when 1 is written to EFR bit in CNTLA register.	
; PE: Parity Error if parity is enabled.
; FE: Framing Error is detected when the Stop bit of a character is sampled as 0 or space.
; RIE: Receive Interrupt Enable must be set to 1 to enable ASCI receive interrupt requests.
; !DCD0
; TDRE: Transmit Data Register Empty, 1 indicates TDR is empty and the next transmit data byte is written to TDR, 
; afterwards it is cleared to 0.
STAT1 		EQU	5	; ASCI Status Register 1.
; 8 bits L to R are: RDRF, OVRN, PE, FE, RE, !----, TDRE, TIE	
TDR0 		EQU	6	; ASCI Transmit Data Registers, sends data to Transmit Shift Register. R/W. Double buffered.
TDR1		EQU	7	; Register addresses 06h and 07h hold the ASCI transmit data for channel 0 and channel 1.
RDR0		EQU	8	; ASCI Receive Data FIFOs, send data by the Receive Shift Register. R. Well buffered.
RDR1 		EQU	9   ; Register addresses 08h and 09h hold the ASCI receive data for channel 0 and channel 1.

CNTR		EQU	0AH	; CSIO Control/Status Register.
TRDR 		EQU	0BH	; CSIO Timer Data Register Channel Low.

TMDR0L 		EQU	0CH	; Timer Data Register 0 Low.
TMDR0H 		EQU	0DH	; Timer Data Register 0 High.
RLDR0L 		EQU	0EH	; Timer Reload Register 0 Low.
RLDR0H		EQU	0FH	; Timer Reload Register 0 High.

TCR			EQU	10H	; Timer Control Register.
; 8 bits L to R are: TIF1, TIF0, TIE1, TIE0, TOC1, TOC0, TDE1, TDE0
; TIF1: Timer Interrupt Flag 1, bit 7, when TMDR1 decrements to 0, TIF1 is set to 1. When enabled by TIE=1 an interrupt
; request is generated. Cleared when TCR is read.
; TIF0: Timer Interrupt Flag 0, bit 6, same but TMDR0 and TIF0.
; TIE1: Timer Interrupt Enable 1, bit 5, when set to 1 TIF1 = 1 generates an interrupt. When r
TMDR1L		EQU	14H
TMDR1H		EQU	15H
RLDR1L		EQU	16H
RLDR1H		EQU	17H

FRC			EQU	18H

SAR0L		EQU	20H
SAR0H		EQU	21H
SAR0B		EQU	22H
DAR0L		EQU	23H
DAR0H		EQU	24H
DAR0B		EQU	25H
BCR0L		EQU	26H
BCR0H		EQU	27H
MAR1L		EQU	28H
MAR1H		EQU	29H
MAR1B		EQU	2AH
IAR1L		EQU	2BH
IAR1H		EQU	2CH

BCR1L		EQU	2EH
BCR1H		EQU	2FH

DSTAT		EQU	30H
DMODE		EQU	31H
DCNTL		EQU	32H
IL			EQU	33H
ITC			EQU	34H

RCR			EQU	36H

CBR			EQU	38H		; MMU REGISTERS
BBR			EQU	39H
CBAR		EQU	3AH

ICR			EQU	3FH